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PLL with Jitter Measurement BIST Disclosure Number: IPCOM000130196D
Original Publication Date: 2005-Oct-17
Included in the Prior Art Database: 2005-Oct-17
Document File: 4 page(s) / 137K

Publishing Venue



The invention comprises a method to measure jitter in a PLL circuit in a serial link. Specifically, the method is implemented as a PLL BIST function that allows the PLL's deterministic and random jitter to be measured. Additionally IP is disclosed to make the jitter monitoring BIST function independent on PVT variations.

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PLL with Jitter Measurement BIST

PLL BIST (phase locked loop built-in self test)


This invention relates to the jitter characterization of a PLL in a serial link.

The performance (=eye width) of a serial link is highly dependent on the jitter generation of its clock generation unit (Tx and Rx PLL & clock distribution network). In a typical link macro each link is operated under its own PVT PVT: process-voltage-temperature variations. conditions which have an impact on the jitter of the clock generation unit. It is therefore important to characterize the jitter generation of the link's PLLs at runtime. Since serial links are highly integrated (#links/macro>10), no external measurement equipment can be used for jitter measurements and the jitter generation of the PLLs is preferentially executed by the PLLs' BIST functions.


This disclosure proposes a jitter characterization method implemented as PLL BIST function that allows to determine the PLL's deterministic and random jitter generation. The method is based on the evaluation of the sample statistics taken from samples of the output signal of the 1/N-divider and the application of a jitter model.

The functional principle of the jitter characterization method is shown in Fig. 1. The jitter analysis is performed at the output of the 1/N-divider as shown in Fig. 1a. It outputs the rms jitter and the peak-to-peak jitter that are produced by the PLL. Note that the specified jitter is referred to the reference signal fref and not to the PLL output signal fRF,out whose phase noise level φRF is higher by 20·log(N) compared with the phase noise level φ1/N at f1/N. The factor N is the division ratio defined as N=fRF,out/f1/N. The rms jitter Jrms can be calculated from the phase noise φ by [1]

J φ



rms )









 df f

, (1)

where f1, f2 define the offset frequency range of interest (with respect to fRF,out).

  out RF



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Fig. 1: Schematic of a PLL with BIST function for the characterization of the PLL's jitter generation.

The schematic of the proposed jitter analysis BIST function is shown in Fig. 1b. The divider output signal f1/N gets sampled by the reference signal fref which was phase shifted by Δϕ with respect to fref at the input of the phase frequency detector (PFD). Note that fref and f1/N are phase aligned in the PFD when the PLL is locked. This fact can now be exploited to analyze the jitter by carrying out the following steps:
(1) Perform a phase shift of fref by Δϕ to obtain f 'ref
(2) Use f 'ref to sample f1/N
(3) Make a decision on whether the sampled value is true or wrong by means of the 'a priori' knowledge of how the correct sample value must look like (because fref and f1/N are phase aligned in the PFD). This results in a sample statistics of the edge positions of f1/N with respect


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to fref. Or in other words: The sample statistics represents the ji...