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Interrupt scheme for universal sensor Disclosure Number: IPCOM000131214D
Original Publication Date: 2005-Nov-10
Included in the Prior Art Database: 2005-Nov-10
Document File: 2 page(s) / 40K

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Interrupt scheme for universal sensor

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Interrupt scheme for universal sensor

Interrupt handling for a core interfacing with a universal sensor and performing post processing on the datastream received from this universal interface is quite complex. Three types of errors could occur :

The first type of error is related to the datastream sampling from the universal sensor

The second one is related to the post processing of the datastream within the core

The last one is related to the post processed datastream transfer to the system

    In such system, the datastream is a consecutive frame stream whatever is the frame containt as soon as the frame is delineated by a Frame start and a Frame end. Due to the fact post processing occurs, the core needs to be able to monitor two frames at a time, with potential errors on both frames:

The frame which is currently sampled by the core

The frame which is currently processed or/and transfered to the system

Having a single interrupt register including status on both frames is not so easy to handle by software. The device driver handling this interface requires to be smart enough to identify within the post processed stream which frame is good or bad. The simplicity of the hardware depends on the coplexity of the software.

    The goal of this new interrupt scheme is to ease the overall system monitoring. The main characteristics is defined by the following considerations :

The interrupt register is doubled in the hardware:

° Current and hidden registers. ° Same address for both registers. The software only sees the current interrupt register.

The current register is handling the status of the frame which is currently post processed by the core or/and transfered to the system The hidden register is handling the status of the frame being currently sampled. The software and not the hardware is responsible to switch software access from one register to the other. It means:

° The current register becomes the hidden one ° The hidden register becomes the current one. Interrupt register switching is performed by writing a b'1' in a specific field of the control register of the core. This writing has also the two following consequences:

    ° Reset of the interrupt register which switch from current to hidden ° Reset of this specific field when the interrupt register switching is completed to reable this mechanism for the next frame. Writing a b'0' has no effect. The interrupt register contains two fundamental fields ("Good frame" and "Bad frame") to indicate the overall status of the frame which has just been transfered to the system.

° These fields are evaluated at the end of the transfer.


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    ° The "Good frame" indicates that no error has been h...