Browse Prior Art Database

A Rescructurable Integratect Circuit for Implementing Programmable Disclosure Number: IPCOM000131479D
Original Publication Date: 1982-Mar-01
Included in the Prior Art Database: 2005-Nov-11

Publishing Venue

Software Patent Institute

Related People

Rob Budzinski: AUTHOR [+4]


[Figure containing following caption omitted: Figure 1. Microprocessor failure rate history.] The RIC is a semicustom IC that serves much the same purpose as gate arrays and masterslices. The gate- array approach allows a logic diagram to be translated into silicon through software. The software creates an interconnect pattern among the gates so that the logic diagram is implemented in silicon. The gate array approach is very flexible, but provides no special structure for implement ing programmable digital systems. The RIC approach uses the large number of gates on a VLSI IC to build a chip that is highly flexible in implementing programmable digital systems. The RIC approach differs from gate arrays in that it commits the vast majority of its silicon to a specific design. RlC's flexibility is achieved through the design of a programmable mechanism for controlling the hardware resources on the chip. A block diagram of the restructurable IC is shown in Figure 2. The RIC is a multimicrocomputer that contains four 16-bit processors called microprogrammable slices, or MPSs. The MPS resources can be controlled at two basic levels. The first level of control is in the coordination of MPSs. The four MPSs can be dynamically configured at runtime into any combination of three fundamental structures. One is the lockstep, in which two or more MPSs are structured to form a wider- word computer. This structure is formed by directing the same microinstruction stream to all of the MPSs in the lockstep and structuring the arithmetic status, carry chain, and shift/rotate linkage to configure the MPSs into a widerword computer. In the second fundamental structure, MPSs are independent; each has its own microinstruction stream. A set of array processors can be structured into the independent configuration by directing the same microinstruction stream to the MPSs, without coordination of arithmetic signals between MPSs. In the third fundamental structure, MPSs are pipelined. Each forms a stage in the pipeline, and the microinstruction streams are different for each stage. An internal data bus within the RIC provides for simultaneous sending and receiving of data between adjacent stages (MPSs) in the pipeline.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 9% of the total text.

Page 1 of 13


This record contains textual material that is copyright ©; 1982 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Contact the IEEE Computer Society (714-821-8380) for copies of the complete work that was the source of this textual material and for all use beyond that as a record from the SPI Database.

A Rescructurable Integratect Circuit for Implementing Programmable

Digital Systems Rob Budzinski, John Linn, and Satish Thatte,

Texas Instruments

RIC, Texas Instruments' restructurable integrated circuit, could be a major step in VLSI technology. Its flexibility promises custom-desicn performance at off-the-shelf cost.

Development of a highly programmable, restructurable VLSI IC is an extremely important step toward effecting maximum impact of VLSI. Not only do programmability and flexibility provide new creative opportunities for the system designer, they help overcome two major obstacles to pervasive use of VLSI: design cost and design cycle time.

Flexibility, reliability, and cost

Typically, a state-of-the-art LSI custom design consisting of 5K gates and 5K bits of read-only memory costs approximately $500 thousand and takes about 18 months to design and lay out. This comesto about $100pergatein the design. If design costs fall an order of magnitude to $10 per gate over the next five years, a t ypical state-o f-t heart VLSI custom system consisting of 50K gates and 50K bits of read-only memory will still cost $500 thousand to design. A very flexible VLSI chip that can be restructured to provide a wide range of capabilities and state-of- the-art performance presents a viable alternative to custom designs in low-veh~me applications.

Reliability, testing, and maintenance considerations are extremely important in complex VLSI systems. Because poor reliability is reflected in the cost of service calls and returned products, it can, over the life of the system, incur costs greater than those of initial manufacturing. Traditionally, reliability has improved with each increase; in the level of integration. However, reliability also benefits from accumulated learning, as shown in Figure I. A generic programmable chip, in this case the Texas Instruments TMS-IOOO microcomputer, increases in reliability as more are manufactured. Although specific programmations of the chip might not be made in significant volume, each programmation benefits from improvements in the reliability of the generic device.

Custom designs, on the other hand, even those using identical processes, do not benefit significantly from the high-volume reliability learning that applies to other chips. A restructurable VLSI circuit will provide a high degree of reliability learning, even if the volume of most programmation types is small.

Overview of the RIC

(Image Omitted: Figure 1. Microprocessor failure rate history.)

The RIC is a semicustom IC that s...