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New scan cell design to reduce scan power consumption and scan time Disclosure Number: IPCOM000131728D
Original Publication Date: 2005-Nov-17
Included in the Prior Art Database: 2005-Nov-17
Document File: 2 page(s) / 53K

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Disclosed is a new scan cell design for level-sensitive scan circuits. This new scan cell provides significant savings in scan power consumption and scan time.

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New scan cell design to reduce scan power consumption and scan time

Power consumption during scan is known to be several times higher than in functional operation because random values are passing through all latches in the design. The logic is subjected to many transitions, which may never occur in functional mode. This can cause chip overheating during scan and destroy the chip. In addition, slow scan cycles (to reduce power consumption), can significantly increase testing time and test cost.

This disclosure introduces a new scan cell design to reduce power consumption during scan and reduce testing time through the use of faster scan clocks. Known solutions to the scan power consumption problem are a) to reduce the speed of scan to reduce scan power consumption, b) to use L3 latches (controlled by a 4th LSSD clock called the P clock) to gate off transitions to logic in scan, and c) to use an AND gate controlled by scan enable to gate off unwanted transitions to logic in scan . The problems with the known solutions are as follows. Firstly, reduction of scan speed adversely impacts test application time and test cost. Secondly, the use of additional L3 latches increases hardware overhead. Finally, an AND gate if added to the output of latches adds delays to the critical path. Hence, a new scan cell design is proposed.

The new scan cell is illustrated in the Figure. Latches in the scan chain must be in order of last L1 latch in scan chain receives A clock pulse f...