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Fabricating Self-Aligned Stacked CMOS Field-Effect Transistors and Logic Devices

IP.com Disclosure Number: IPCOM000132325D
Publication Date: 2005-Dec-07
Document File: 3 page(s) / 209K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a totally self-aligned, gate-last process compatible with novel gate electrodes and dielectrics (e.g. metal gates and high-k dielectrics). Benefits include improved flexibility to individually optimize channel doping, chemical composition, and strain conditions.