Fabricating Self-Aligned Stacked CMOS Field-Effect Transistors and Logic Devices
Publication Date: 2005-Dec-07
The IP.com Prior Art Database
Disclosed is a method for a totally self-aligned, gate-last process compatible with novel gate electrodes and dielectrics (e.g. metal gates and high-k dielectrics). Benefits include improved flexibility to individually optimize channel doping, chemical composition, and strain conditions.