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Self-Aligned SiO2 Barrier / CMP Polish Stop for BEOL Wiring in Polyimide Dielectric Disclosure Number: IPCOM000132330D
Original Publication Date: 2005-Dec-07
Included in the Prior Art Database: 2005-Dec-07
Document File: 4 page(s) / 371K

Publishing Venue



A methodology for creating a wiring pattern or inductor in a polyimide material by damascene processing is enabled with use of a polyimide film which contains a bulk Silicon-based adhesion promoter. There are standard commercially available materials, like HD4000 PSPI (photosensitive polyimide) which can be used. After creating the wiring pattern in the polyimide material, the surface is treated with an O2 plasma ash or RIE process which causes surface formation of a silicon dioxide film by reaction of the silicon in the bulk film with the oxygen in the plasma. This SiOx film is then used as a polish stop for chem-mechanical polishing (CMP) of the wiring metalization after a bulk electroplating step.

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Self-Aligned SiO2 Barrier / CMP Polish Stop for BEOL Wiring in Polyimide Dielectric

Organic spin-on polyimide materials have excellent dielectric properties, but their material softness generally precludes use in the fabrication of modern copper wiring levels in integrated circuit products. Copper wires are normally fabricated by plating copper in trenches that are created by photo-patterning and RIE, and then planarizing the surface with a chem-mechanical polish (CMP) process that physically separates the wires by vertical removal of plated copper down to the level of the top of the wiring trenches. Hard-dielectric materials like SiO2, FTEOS or FSG are standard, and newer "lowK" dielectrics must be hard enough to withstand the physical forces of CMP.

Polyimides are a class of organic polymers typically used in the semiconductor industry as a chip-level final surface passivation material or a packaging laminate material where features do not require more planarization than is provided by an organic spun film.

It has always been of interest to use polyimide materials in the BEOL as a wiring dielectric, because of their unique qualities of low dielectric constant, process simplicity, low cost, natural planarization tendency, and post-cure stability. However, their inherent softness makes them incompatible with CMP, which is required for the fabrication of multi-level BEOL wiring in today's ICs.

The core of the invention is to use a photosensitive polyimide (PSPI) with a built-in silicon-containing adhesion promoter, to create CuBEOL wiring, by taking advantage of an extended (surface) O2 ash process after the PSPI pattern step, to create a self-aligned SiO2 capping layer to protect the PSPI during CMP.

There is at least one PSPI material that is commercially available today for which this SiO2 layer can easily be formed in this manner, to a thickness of ~100nm (Figure 1). It is clearly shown that a ~100nm "crust" of SiO2 material is formed during O2 ash of this material. It has been established that this occurs from reaction with the built-in bulk film adhesion promoter, which is an ethoxysilane-type material (like A1100).

Figure 1. FIB Cut showing SiO2 crust on polyimide.

FIB Cut revealing PSPI thickness