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Method for Testing Scan Controls and Power Saving Circuits in a Pipelined Design Disclosure Number: IPCOM000132346D
Original Publication Date: 2005-Dec-08
Included in the Prior Art Database: 2005-Dec-08
Document File: 2 page(s) / 28K

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Disclosed is a method for testing pipeline control signals and power saving devices in the cell microprocessor. The faults in these structures are not directly observable. Therefore, a conditioned shift is used to indirectly observe these faults.

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Method for Testing Scan Controls and Power Saving Circuits in a Pipelined Design

In a high speed microprocessor, control signals and clock gating signals are typically pipelined to allow for even distribution across the chip. These control pipelines are quite extensive (28 stages for this design). These structures are used for testing target logic and programming BIST engines. These signals are also implemented as power saving devices. They gate clocks to certain registers and reduce switching between test-only paths, resulting in less power consumption. Disclosed is a method for testing these structures in the Cell microprocessor.

During each stage of the pipeline, the scan controls may be gated by different control signals and control registers. Many faults on these pipelines can be tested by the proposed technique, but not tested with conventional structural tests.

The difficulty in testing these structures is that these faults are not directly observable, since access to these areas is not permitted by normal scanning. The faults are observed by whether or not a shift is performed in the normal scan chains holding 010101...

The advantage of this invention is that higher fault coverage can be achieved when this test is included in a testflow than not. Also, these power saving features will be guaranteed to work, resulting in lower power consumption during operation.

Steps for testing a scan control signal:
1. Fill all scan chains which are affected by the scan control pipe...