Automatic generation of partial-good embedded memories for SoC's
Original Publication Date: 2005-Dec-28
Included in the Prior Art Database: 2005-Dec-28
An automated method for generating partial-good embedded memories is proposed. The new method enables parallel module-level (or post-fuse) BIST testing of multiple embedded memory instances on the SoC/ASIC die, where each memory instance can be of a unique size and all can possess different partial-good solutions.
Automatic generation of partial -good embedded memories for SoC 's
Historically, memory yields have been improved by using redundant elements to replace failing regular elements. However some memories may be unrepairable due to a large localized defect which creating a plurality of failing elements exceeding the amount of redundancy available. These chips may often be used as a partially-good chip with a decreased address space (i.e. an unrepairable 64Mb chip could be used as a fully usable 32Mb chip.) This increases the number of chips that can be used in a system. The generation of these partial-good chips is accomplished by using external equipment testing the memory chip and separating the known bad die with localized fail signatures (those that can be used as a 1/2 good or 1/4 good, as opposed to having a large amount of scattered fails rendering the chip unusable) from the passing die. A repair solution is then generated to create the partial-good address space which is then fused to permanently reconfigure the chip.
As integration of integrated circuit function has progressed, memory structures are being placed on the same die as that of a sytem processer. Integrating the memory into the logic introduces new challenges particularly in the areas of memory test and repair. With Built-In Self-Test (BIST) becoming the predominant method of testing embedded memories, comprehensive testing of the memory has been essentially solved. Recent advances in BIST include Built-In Self-Repair (BISR) capabilities, which use the results of the BIST sequence to replace the failing elements with the redundant elements.
BISR does not enable the reconfiguration of an embedded memory with a single, large, localized defect. This type of defect will require more redundant elements than are available and can render an entire SoC useless as there is no way to generate a partially-good memory on board. Not only do current BIST engines and BISR circuits lack the capability but there is no way to reconfigure the logic around the memory to take advantage of the partially-good memory.
We propose an automated method of generating partial-good embedded memories. In addition, the method we propose enables parallel module-level (or post-fuse) BIST testing of multiple embedded memory instances on the SoC/ASIC die, where each memory instance can be of a unique size and all can possess different partial-good solutions.
The advantages of the invention include (but are not limited to): More die for early life hardware characterization (when yields are typically low and the number of parts is limited) and more die that can be used in the system. The granularity of this system is also much better than that of previous methods (OLD:1/2 good, 1/4 good; NEW 15/16 good, --> 1/16 good). Also, by automating the generation of partially-good chips, no interaction with external test equipment is necessary, reducing the capital overhead of the ATE. Our method also fuses the...