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Clock Feedback Divider and Alignment Detector for Multi-Cores

IP.com Disclosure Number: IPCOM000133375D
Publication Date: 2006-Jan-25

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a multi-core CPU with multiple phase locked loops (PLL) and multiple clock domains. The disclosed method uses a special scheme to synchronize the clock in each clock domain. Benefits include allowing two buses to operate at odd ratios, while eliminating any uncertainties between them.