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A MULTI-CHANNEL DMA MODULE FOR STREAMING COMPUTATIONS

IP.com Disclosure Number: IPCOM000133577D
Original Publication Date: 2006-Jan-31
Included in the Prior Art Database: 2006-Jan-31

Publishing Venue

Motorola

Related People

Authors:
Nikolaos Bellas Sek Chai Malcolm Dwyer Dan Linzmeier

Abstract

Multimedia SoCs process high resolution images at a high frame rate. In a lot of cases, these systems are limited not by the lack of computational power of the processors, but by lack of bus or memory bandwidth when data are transferred between the image sensor, the main memory and the processing elements of the system. This paper describes an extended DMA design which can also execute simple streaming kernels on the data that are passing through. Multiple DMAs that are able to transfer streams and apply simple filtering operations on them can offload both the processing elements from excessive computations and the bus and main memory because they eliminate wasteful data transfers.