Browse Prior Art Database

Method for Test Pattern Generation from Previously Verified Results Databases

IP.com Disclosure Number: IPCOM000138747D
Original Publication Date: 2006-Jul-31
Included in the Prior Art Database: 2006-Jul-31
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Abstract

The disclosure proposes an addition to the current manufacturing test pattern generation flow. This addtion to the flow solves the current problems and limitations, as mentioned in the text below, by including the existing verifciation, and other related, results databases to generate the patterns.

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Manufacturing test, used to find out module/chip manufacturing faults (like open connections, noisy lines, functional failure etc), are executed by applying "patterns" to the input pins of the module/chip and observing the output pins. The patterns are generated by pattern generation tools (like TestDE by Cadence design systems).

    Pattern generation tool though capable of generating quite sophisticated patterns, still requires a basic sequence that acts as a starting point for all the patterns to be generated. Frequently this sequence is an initial part of the Power on Reset (POR) sequence that puts DUT into a state where it can recognize and run the "patterns" appropriately. Since the pattern generation tool does not have any information other than the scan chain structure of the DUT, this sequence has to be hand generated by the DFT engineer and then fed to the patterns generation tool which makes the process error prone and iterative.

    Another problem arises when the patterns generated by the pattern generation tool cannot be run "as is" by the TESTER on the hardware due to logic failures, "manufacturing tester failure" or timing failures in the logic. For e.g., a timing failure can prevent parts of logic to be scanned and/or hold on to some specific values, which is required to enable the DUT to be able to accept and run subsequent patterns. Generally the DUT provides alternative way(s) of setting up the failing parts of logic but the pattern generation tool cannot utilize them as these setup operations require different set of sequences to be executed/run on the DUT I/Os, which the pattern generation tool has no inherent knowledge about.

    The following diagrams show the current and the proposed method to generate and debug "patterns".

This invention adds another path in the "manufacturing test pattern" flow that would enable additional/alternative ways to generate patterns for the TESTER when pattern failures cannot be corrected by regeneration with the current tool. It also provides a mechanism to generate supplemental "patterns" for the current generation tool to create more complex patterns. It also utilizes the aforementioned method to automate the generation of base POR sequence for the pattern generation tool from a previously verified simulation testcase result database.

As is shown in the current flow there are two areas of concern:
1. If the failure analysis indicates that the pattern generated by the pattern generation tool cannot work "as is" and requires an alternative way to execute operations to ...

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