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Method for scanning low-voltage differential signals Disclosure Number: IPCOM000146259D
Publication Date: 2007-Feb-08
Document File: 6 page(s) / 473K

Publishing Venue

The Prior Art Database


Disclosed is a method for scanning low-voltage differential signals. Benefits include improved test environment and improved reliability.

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Method for scanning low-voltage differential signals

Disclosed is a method for scanning low-voltage differential signals. Benefits include improved test environment and improved reliability.


      Low voltage swing (LVS) circuits do not have state elements, such as latches or flip-flops.  Converting to scan cells or inserting scan cells for testing is impractical. As a result, functional testing is performed on these circuit blocks. By writing assembly language architectural tests, some coverage may be provided. However, fault grading and subsequent additional test writing is required to bring the coverage up to an acceptable level, which consumes additional resources.

         An ideal scan test system has scan elements located at the block’s input and output (see Figure 1). Control signals should also be under scan control. If the state space inside the block is limited, most sequential automated test program generation (ATPG) tools can generate tests that provide reasonable coverage.

      A scan system typically processes digital information, where a high voltage level above logic threshold represents a 1, and a low voltage level below logic threshold represents 0. Typically, a relatively wide voltage margin occurs between 1 and 0. For LVS logic, the logic levels are represented by a small 50 mV through 150 mV differential. Therefore, differential signals are used. The small differential signal pairs represent logic. Any one of these signals does not represent the logic level because the absolute voltage levels are so close together. To increase noise immunity with a falling VCC trend, more signals are differential in nature, even though they may not be small swing level.

      Circuits without state elements, like latches or flip/flops, are reset at the beginning of the compute cycle. Previous data are sent in and operated on. The results are passed onto the next stage for another set of computations. The data are not kept in the execution pipeline, so conventional scanning techniques, such as converting state elements to scannable elements, do not work.

General description

      The disclosed method is a scan test method for low-voltage differential signals. The key element of the method is the handling of small swing differential signals in a scan test system.


      The disclosed method enables scan testing for LVS circuits, so that the scan test is uniform over the entire chip.

Detailed Description

      The disclosed method provides control of structural testing. State element equivalent circuits are identified within the LVS circuits. The keeper cell (see Figure 2) does not store dat...