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A Method to Assemble a Flip Chip Electronics Package with Fluxing Underfills Disclosure Number: IPCOM000149686D
Original Publication Date: 2007-Apr-04
Included in the Prior Art Database: 2007-Apr-04
Document File: 2 page(s) / 35K

Publishing Venue



A novel assembly methodology, using fluxing underfills, is disclosed for flip chip electronics packages. The unique methodology addresses the industry-wide challenges associated with filler entrapment, voiding, sub-optimal underfill material properties, low k and ultra-low k dielectric assembly processes, and process optimizations/simplifications.

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A Method to Assemble a Flip Chip Electronics Package with Fluxing Underfills

The applicability of fluxing underfills to flip chip packaging has been limited. Issues such as filler entrapment, voiding, and sub-optimal underfill material properties are some factors that, to date, have prevented pervasive use of fluxing underfills for flip chip assembly. The novel assembly method under discussion circumvents the issues that,
to date, have hindered the ubiquitous administration of fluxing underfills to flip chip packaging. A depiction of this novel assembly method is presented in the diagram below.

Please note, we intend the terms chip(s) and device(s) to be interchangeable.

In step 1, we start with a chip carrier. The chip carrier in the diagram indicates solder on the chip carrier bonding pads. This is not a necessity, as it will depend largely on the application, material-set, and solder hierarchy.

In step 2, we apply Fluxing Underfill 1 (FUF1). The FUF1 can be applied to the chip carrier with a screening operation. FUF1 can also be applied to the chip(s), which are to be placed on to the chip carrier, with a dip operation. Other methods may also be employed.

In step 3, we place the chip(s) on to the chip carrier. FUF1 provides adequate tack to prevent chip misalignment. We next apply Fluxing Underfill 2 (FUF2) via capillary action.

In step 4, we illustrate an assembled flip chip package. In this illustration, the package has been assembled using FUF1 and FUF2. The FUF1 is applied to the bonding arrays of the chip(s) and/or chip carrier bonding pads. FUF2 is applied, via capillary action, to fully encapsulate the gap between the chip(s) and chip carrier. If desired, after the capillary application...