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Synapse: Method for converting XDR write mask to DDR2/3 write mask

IP.com Disclosure Number: IPCOM000149832D
Original Publication Date: 2007-Apr-09
Included in the Prior Art Database: 2007-Apr-09
Document File: 2 page(s) / 32K

Publishing Venue



Disclosed are the mechanisms to convert an XDR write mask command into the appropriate signals to drive and perform a masked write on a DDR2/3 interface. This is useful for a XDR to DDR2/3 conversion chip.

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Synapse: Method for converting XDR write mask to DDR 2/3 write mask

XDR (eXtreme Data Rate) memory systems provide high memory bandwidth by sending eight data bits per clock cycle over an XIO (eXtreme IO) link, from a memory controller to the XDR DRAMs. An XIO link is capable of achieving signal rates of 3.2 Gbps and above, allowing a memory controller to use fewer I/O and therefore save on die size and cost.. However, due to reasons both technical and financial, XDR memory systems are limited in the amount of memory capacity they can support. XDR memory is also more expensive than industry standard memories such as DDR2. In order to use a chip with an XIO interface in an application which requires large amounts of memory, a bridge/hub chip is required which converts the XDR command and data protocols to the DDR2 command and data protocols. This solution maintains the advantage of using the XIO link (fewer pins on the expensive memory controller), but enables the advantages of DDR2 (low cost, high capacity).

In order to keep the pin count low, XDR supports the ability to mask bytes from being written by including a mask in a special write command. The mask is a single byte data pattern, which if detected in the write data, results in that byte not being written to memory.

    The challenge for an XIO to DDR2 bridge chip is to convert the XDR masked write command to the write mask lines on the DDR2/3 interface. This invention solves the problem of taking an...