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AUTOMATIC RANDOM LOGIC LAYOUT SYNTHESIS - A MODULE GENERATOR APPROACH

IP.com Disclosure Number: IPCOM000151785D
Original Publication Date: 1986-Dec-31
Included in the Prior Art Database: 2007-Apr-23
Document File: 155 page(s) / 5M

Publishing Venue

Software Patent Institute

Related People

Yu, Meng-Lin: AUTHOR [+1]

Abstract

Report No. UIUCDCS-R-86-1244 AUTOMATIC RANDOM LOGIC LAYOUT SYNTHESIS A MODULE GENERATOR APPROACH MENG-LIN YU B.S., National Taiwan University, 1980 M.S., University of Illinois, 1984 THESIS Submitted in partial fulfillment of the requirementsfor the degree of Doctor of Philosophy in Computer Science in the Graduate College of theUniversity of Illinois at Urbana-Champaign, 1986 Supported in part by the National Science Foundation Grant MCS 82-18104 and IBM Corporation. Urbana, Illinois ACKNOWLEDGEMENTS First, I would like to thank my thesis advisor Professor William Kubitz for his advice, guidance, patience, and sincere interest in this research. I would also like to thank my friends at University of Illinois and the faculty/staff of the Department of Computer Science for indirectly contributing to this thesis through friendship and support throughout my stay in Illinois. Special thanks go to my colleagues, Yu-Chin Hsu, Forrest Brewer, and Steve Healey for discussions concerning the research topic. I would also like to thank my wife Yi-Ling Yan for preparing most figures.

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Report No. UIUCDCS-R-86-1244

AUTOMATIC RANDOM LOGIC LAYOUT SYNTHESIS

- A MODULE GENERATOR APPROACH

MENG-LIN YU


B.S., National Taiwan University, 1980

M.S.,

University of Illinois, 1984

THESIS

  Submitted in partial fulfillment of the requirements
for the degree of Doctor of Philosophy in Computer Science in the Graduate College of the
University of Illinois at Urbana-Champaign, 1986

Urbana, Illinois

Supported in part by the National Science Foundation Grant MCS 82-18104 and IBM Corporation.

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ACKNOWLEDGEMENTS

   First, I would like to thank my thesis advisor Professor William Kubitz for his advice, guidance, patience, and sincere interest in this research. I would also like to thank my friends at University of Illinois and the faculty/staff of the Department of Computer Science for indirectly contributing to this thesis through friendship and support throughout my stay in Illinois.

   Special thanks go to my colleagues, Yu-Chin Hsu, Forrest Brewer, and Steve Healey for discussions concerning the research topic. I would also like to thank my wife Yi-Ling Yan for preparing most figures.

   Finally, most heartfelt thanks go to my parents, Ruey-Jane Wang, and Yi-Ling Yam. Without their love, sacrifices, and spiritual support at all the time, it would be impossible for me to finish this thesis.

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TABLE OF CONTENTS

CHAPTER

....................................................................

1.1. VLSI Layout Methoda ...................................................................................

..................................................

1 . INTRODUCTION .......................... ..

1.2. Silicon Compilation and Module Generators

1.3. Thesis Overview

............................................................................................

2 . SYSTEM ENVIRONMENT AND METHODOLOGIES

..........................................


2.2. Virtual Grid Layout Subsystem ....................................................................

2.3. Random Logic Module Generator Subsystem ........................................& ........

2.1. System Philosophy and Methodologies

..........................................................

3 . PARTITlONING WITH PLACEMENT AND GLOBAL WIRING

ASSIGNMENT ......................................................................................................

3.1. Two-Dimensional Partitioning Algorithms ....................................................
.....................................................................

3.2. Interfacing the Cell Synthesizer


4 . CELL SYNTHESIS ................................................................................................

4.1. Synthesis Models

..........................................................................