Method for Analyzing Single-via (or contact) Interface at a Specific Failure-Site in an Integrated Circuit
Publication Date: 2007-Oct-31
The IP.com Prior Art Database
This publication presents a method for analyzing a single-via (or contact) interface at a specific failure-site in an integrated circuit. The method enables us to precisely locate and prepare a specific fault-isolated feature (e.g., single-via or contact site) for Scanning Auger (or other) analysis to enable identification of the material/s in a residual film (at the via or contact interface) that caused the single-via (or contact) to fail.