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Use of Virtual ECC to Protect Arrays in a Hardware Simulation Accelerator Disclosure Number: IPCOM000167585D
Original Publication Date: 2008-Feb-21
Included in the Prior Art Database: 2008-Feb-21
Document File: 1 page(s) / 25K

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The memory used to model user arrays in hardware simulation accelerators is not always protected with ECC, or even parity. If it is later determined that the soft error rate is too high, virtual logic can be added around the array ports, and with appropriate support from the runtime, provide the same protection that a hardware implementation provides.

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Use of Virtual ECC to Protect Arrays in a Hardware Simulation Accelerator

The AwanNG hardware simulation accelerator uses external SRAM to model user arrays. A parity bit is used to detect soft errors in this external SRAM. Although the overall soft error rate is low, each error causes an unrecoverable interruption to the user simulation, and the user might lose hours of simulation time. At one time, we experienced surges of errors where we would encounter several soft errors within a week, and we started to regret that we hadn't implemented hardware support for ECC around these SRAMs.

A solution to this problem is to use virtual ECC. By using virtual logic to add ECC around each user array read or write port, any soft errors can be corrected and will not affect the user in any way.

During model build time, user arrays are extended with ECC bits. ECC generation logic is added to each write port, and error correction logic is added to each read port. When the runtime writes to an array, it also generates the ECC bits. When the runtime reads an array, it could either always apply error correction, or it could choose to only apply error correction if a parity error is detected by the hardware. If a parity error is detected during simulation, the runtime can determine the bad array location, correct the error, and resume simulation. The ECC bits are removed before presenting array data to the user, so this would not affect the...