Circuit to Limit Effect of OCV (On Chip Variation) and Improve Performance of Clock Distribution Networks
Publication Date: 2008-Jul-23
The IP.com Prior Art Database
With hundreds of millions of transistors being integrated on a single chip, a clock distribution network with near zero skew is a great challenge. For high performance wireless designs, power and speed are critical factors. High speed (GHz) can only be achieved at near zero values of skew. General design practises employ the use of power gating (sleep transistors) and clock gating to reduce system power but these practises limit clock balancing implementations and hence the overall skew and OCV effects increase, which degrades system performance.