Method for a Power Test Screen of a Semiconductor Device Tested at Two Temperatures
Original Publication Date: 2008-Nov-12
Included in the Prior Art Database: 2008-Nov-12
This invention is a method for setting a power measurement screen for semiconductor devices tested at two different test temperatures using IDDQ measurements, with a delta IDDQ measurement used at the lower test temperature.
Method for a Power Test Screen of a Semiconductor Device Tested at Two
The invention is a method that allows for an improved correlation for setting quiescent current
power screen limits between a test taken at two temperatures(semiconductor wafer and
module) by using an optimized dual voltage difference when taking the IDDQ reading at the
lower temperature. This improved correlation is due to reducing leakage in the semiconductor
caused by device variation in gate oxide thickness. This allows for the device variation to be
accounted for insitu instead of having to provide these data to the tester separately. By
improving the correlation between the two IDDQ tests, a yield improvement is seen at both tests
resulting in cost savings by:
Not failing wafer die that would pass at module test(loss die cost)
Not building wafer die that fail at module test(loss module package costs)
This invention uses IDDQ testing for power screening where as previous publications use IDDQ
testing for defect detection only.
Description of Method
Method for setting a power screen limit for testing a semiconductor device at two temperatures
by using quiescent current (IDDQ) and a dual voltage delta comprising the steps of: measuring a first quiescent current at a first voltage at a first lower temperature; (wafer below) measuring a second quiescen...