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Improved Wafer Pattern uniformity by selective removal of features for wafer characterization Disclosure Number: IPCOM000177846D
Original Publication Date: 2009-Jan-06
Included in the Prior Art Database: 2009-Jan-06
Document File: 3 page(s) / 63K

Publishing Venue



Attached within is a method and structure for minimizing effects of pattern non uniformity on step and repeat patterns, such as semiconductor chips on a wafer, where only some of the repeated features serve a function related to the positive functioning of the final integrated circuit. Depending on the polarity of the photoresist used, methods are provided for secondarily adding or deleting extra features to preserve pattern density homogenity on a wafer-basis.

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Improved Wafer Pattern uniformity by selective removal of features for wafer characterization

Disclosed within is a system (method and structure) for minimizing the effects of pattern non-uniformity incurred during normal wafer processing. In normal wafer processing, the chip(s) are surrounded by a "kerf" or "scribe line" in which the normal layout groundrules can not be adhered to in order to support test macros, alignment structures, or other manufacturing aids. Typically, these test macros or alignment structures are only measured or used on a subset of the chips they are placed on; every chip and kerf is by definition nominally identical due to the "step and repeat" lithographic method commonly employed in semiconductor manufacture. The invention described below discusses a method for either adding extra features (negative resist), or removing dummy features (positive resist) with a second exposure. This also applies to non-kerf elements that have deleterious effects on the pattern uniformity


Some structures in the KERF and testsites require areas which have very low or very high density of some semiconductor levels, including PC(gate), RX(active), PC+RX, BEOL(metallization). This creates non-uniformity which may impact the subsequent processing (lithography, etch, planarization, anneal) on nearby circuits, which may degrade yield and performance.

Proposed Solution:

Alignment example: Use "fill" to bring the problem area's back to target densities; this "fill" is composed of dummy features with no function other than to modify the pattern density uniformity. With the Fill in some of the test structures or manufacturing aids, they may be deleterious to the functioning, thus this invention provides a method to remove these extra features only where they are necessary. To process this optimized design, the modified mask design is used Expose the wafer as usual. With resist still on the wafer prior to chemical "develop" (crosslinking), a second exposure is completed on a subset of the fields to "expose away" the fill marks for the few test structures, alignment marks, or manufacturing aids that will be used on that wafer. Most marks on the wafer are not used and can be left filled. By leaving the fill in the majority of the regions, the overall pattern density homogenity is preserved which reduces overall process variation and thus electrical performance degradation.

Testsite example: A similar technique can be employed for testsites (unique semiconductor patterned designed for process diagnostics and characterization, rather than for creating functional I/C devices). In this example, the base design is modified with "fill shapes" to correct the pattern non-uniformity inherent to testsite designs (due to needs for probe-ability, electrical isolation, optic...