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Method and Apparatus to Use SSD Controller Expansion Device to Assist in Re-Mapping Bad Data Blocks. Disclosure Number: IPCOM000180809D
Original Publication Date: 2009-Mar-17
Included in the Prior Art Database: 2009-Mar-17
Document File: 4 page(s) / 49K

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In a redundant controller configuration use array expansion device to remap block if re-write attempts fail.

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Method and Apparatus to Use SSD Controller Expansion Device to Assist in Re-Mapping Bad Data Blocks.

In a flash array component failures will occurs in which the block write fails due to localized cell failures in the silicon. The standard practice is for the controller to use a free block and re-map the data to that location. This article describes delegation of the re-map function to an array expansion device.

In a dual controller flash memory array a "smart" flash expansion mux is needed to share an array of flash devices efficiently. When writing to a device it often desirable to read back the data to verify that the write completed and the data stored in the flash device is as intended. A system diagram of a dual SSD controller system and SSD expansion devices is shown in Figure 1..


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Fig. 1 dual controller SSD / Flash expansion network

Device array

Data / control


Controller A

SSD / Flash expansion Mux

Mux enables

Mux enables

Multiple Instances

Data / control


Controller B

Device array

SSD / Flash expansion Mux

Figure 2 shows the internal function blocks of the expansion device. Internal to the flash expansion mux buffer space is provided for the page data of the write operations in progress in the flash devices it services. A history of the writes in progress is maintained. Once the expansion device has determined that a write is complete, a read of the page is performed and compared bitwise to the data stored in the expansion device buffer. Write complete status is delayed until compare operation is complete. In the case of mis-compare The expansion device utility controller will attempt to re-write the data. It is important to note that the flash erase state is a logical '1' in all memory cells. During the compare operation if any data read back is a logic '0' that should have been writte...