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Method for Dynamic Test Binning of Semiconductors Containing Memory Arrays Disclosure Number: IPCOM000181820D
Original Publication Date: 2009-Apr-14
Included in the Prior Art Database: 2009-Apr-14
Document File: 4 page(s) / 74K

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A method of assigning a Selective Reliability Bin (SRB) to a given semiconductor based on criteria obtained during test and/or processing of the same chip. The criteria may be singular, or an algorithm with many inputs. The method of recording the SRB of a given chip may be using, but not limited to, reserved Electronic Chip Identification (ECID) bits.

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Method for Dynamic Test Binning of Semiconductors Containing Memory Arrays

This invention provides a means to dynamically assign a semiconductor IC a risk level as a result of information obtained during Test and/or Processing.

Once this risk level is assigned, it allows for intended steering of a given chip to the appropriate risk level application.

High risk chips go to applications that can tolerate them, low risk chips to applications which require lower fail rates.

Current sorting methods focus on power and performance sorting;

These involve methods to determine, using a combination of voltage, frequency, temperature and test stimuli, whether a given chip will perform at an acceptable target frequency or power under specific conditions.

The method proposed assigns a reliability bin (Selective Reliability Binning "SRB") based on various criteria, and stores the bin information in reserved ECID bits.

Criteria to determine Reliability Binning:

   The Selective Reliability Binning criteria can be determined by, but not limited too, the following:

The number of repairs on chips containing memory arrays.

Leakage current

Low Voltage operating margin

Voltage Screen Kills on a wafer.

Process Health of Line Monitors


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Fig: 1: Generic Test Methodology if Criteria is Memory Repairs

Chip health is determined using a well defined test methodolo...