Automatic Detection and Control of Foreign Objects or Insufficient Clearance in Test Fixtures 03-02-09 -- changed to defensive publication.
Publication Date: 2009-Apr-21
The IP.com Prior Art Database
Automatic Detection and Control of Foreign Objects or Insufficient Clearance in Test Fixtures
Semiconductor and electronics manufacturing processes involve many automated In-Process testings, such as In-Circuit-Testing (ICT), in addition to End-Of-Line (EOL) testings after assembly of components, modules or subsystems.
During continuous assembly processes of Printed-Circuit-Boards (PCBs) and associated automated ICTs (Figure 1), if a foreign object is trapped in a test fixture, it may apply an unintended pressure onto the components or devices being tested, deform the weakest materials/structures within/around the components or at the component-PCB interfaces, i.e., solder joints, and consequently create micro-cracks within the solder joints in addition to other potential damages. These micro-cracks and other potential structural damages are typically latent defects because certain connectivity between the components and PCBs still exists owing to the partial contact at the solder joints, allowing the components with the micro- cracked solder joints escape the In-Process testings and even EOL testings after final assembly.
Loose Component Trapped in Test Fixture Loose Component Trapped in Test Fixture
Figure 1. Schematics of (a) initial and (b) normal testing set ups with intended ideal function, and (c)-(d) unintended error states
Figures 1 (a) and (b) schematically depict the initial and normal testing set ups, respectively, with an exemplary test fixture for ICT, per design intent. In Figures 1 (a) and (b), tPCB is the designed travel distance of a PCB to the ICT fixture, and cIC-TF is the designed clearance between the ICT fixture and an Integrated Circuit (IC) that is soldered to the PCB and being tested along with other components. Under
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Top Surface of Fixture
designed conditions, this clearance is maintained (Figure 1 (b)) and the automated ICT is performed continuously in intended ideal function state.
Figures 1 (c) and (d) schematically show the unintended error states with an exemplary test fixture for ICT, wherein a loose component is accidentally trapped in the test fixture at two exemplary locations, respectively. In Figures 1 (c) and (d), the solid-line circles denote the deformed IC leads and micro- cracked solder joints between the leads and PCBs, whereas the dashed-line circles indicate the potential damages to the ICs at highest stress locations and/or weakest materials/structures.
During continuous manufacturing processes of semiconductor or electronic devices, such as IC components, the associated In-Process testings may also cause latent defects in the components. For example, micro-scratches may be created on wafers (dies) during automated wafer testing, as illustrated in Figure 2. Figures 2 (a) and (b) schematically depict initial and normal...