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Hybrid Memory DIMM That Contains Mainstream DRAM With a Secondary DRAM Type to Allow Higher Capacity at Lower Power

IP.com Disclosure Number: IPCOM000182374D
Original Publication Date: 2009-Apr-28
Included in the Prior Art Database: 2009-Apr-28
Document File: 1 page(s) / 25K

Publishing Venue

IBM

Abstract

Described is an invention that allows for a memory dimm to be constructed with a combination of DRAM and Flash memory (or any other higher density memory technology) without physically using any additional processor pins of physical space in the system package.

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High-end computer systems are having issues with supporting enough memory bandwidth and capacity given constraints in system size and power. DRAM architecture is not keeping up with the progress in CPU capability, and a method is needed to get a secondary level of high-capacity, low power memory in close to the processor to allow the system being built with enough close memory to meet performance objectives. The issues with adding another level in the memory structure is that adding the access points to the processor designs for this higher density memory generally results in less bandwidth from the main memory in the system design.

    This invention allows for a memory dimm to be constructed with a combination of DRAM and Flash memory (or any other higher density memory technology) without physically using any additional processor pins of physical space in the system package.

    In general, high-end memory subsystems use some type of fully buffered dimms to support the bandwidth and capacity necessary in a computer system. This invention adds an additional port to the back side of this buffer chip to support flash memory. This port will be used as backing store for the DRAM on the dimm so that blocks of memory can be moved between the DRAM and the Flash without transferring the data across the memory channel. Transfers...