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A MOSFET-ONLY SELF-BIASED BANDGAP VOLTAGE REFERENCE

IP.com Disclosure Number: IPCOM000183090D
Publication Date: 2009-May-14
Document File: 5 page(s) / 218K

Publishing Venue

The IP.com Prior Art Database

Abstract

Nowadays, the bandgap voltage reference is the wide-spread used circuit in most high end SoCs (System on a Chip). However, frequently one cannot account on the elemental devices that typical bandgap realizations demand or even area, current consumption and noise performance may result compromised. The present approach: eliminates the need of resistors, which not only demands area but also favor noise coupling. Also, it does not need bipolar transistors (BJT). Forward-biased parasitic PMOS back-body diodes are used instead. Process variations can be compensated by trimming, as in any bandgap reference, and it can be accomplished by choosing the appropriate current mirrors ratios among a discrete set, instead of changing resistive ratios. This proposal is valid for low and high headroom voltage, standard and non standard CMOS technologies. In general, the circuit does not need a start-up module unless a short start-up time is needed.

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A MOSFET-ONLY SELF-BIASED BANDGAP VOLTAGE REFERENCE

Abstract: Nowadays, the bandgap voltage reference is the wide-spread used circuit in most high end SoCs (System on a Chip). However, frequently one cannot account on the elemental devices that typical bandgap realizations demand or even area, current consumption and noise performance may result compromised. The present approach: eliminates the need of resistors, which not only demands area but also favor noise coupling. Also, it does not need bipolar transistors (BJT). Forward-biased parasitic PMOS back-body diodes are used instead. Process variations can be compensated by trimming, as in any bandgap reference, and it can be accomplished by choosing the appropriate current mirrors ratios among a discrete set, instead of changing resistive ratios. This proposal is valid for low and high headroom voltage, standard and non standard CMOS technologies. In general, the circuit does not need a start-up module unless a short start-up time is needed.

1. CIRCUIT DESCRIPTION: Figure 1 a) shows the self-biased bandgap reference. Parasitic back-body diodes of PMOS transistors (MD1 to MD3) are used instead of BJTs, as indicated in figure 1 b). MD2 is “a” times up-scaled with respect to MD1 and MD3. Cascode PMOS mirrors ensure good power supply rejection on one hand, while minimizing systematic mirroring errors, on the other hand. All transistors work saturated in Strong Inversion (SI). The current I in the central column and its scaled versions (I1=mI and I2=nI) are internally generated, in a way that the Gate-Voltage-Overdrives (GVO=Vgs-Vth) of M4 and M3 result proportional to the thermal voltage Ut=kT/q while eliminating the dependency of the GVOs on NMOS mobility mn, without caring of the mn temperature behavior law. Assuming, GVOM4 > GVOM3, VBG becomes thus the sum of Vbe2 (decreasing with T) and a PTAT (Proportional-To-Absolute-Temperature) voltage equal to (GVOM4 - GVOM3), as required for any bandgap-like voltage reference. However, this configuration is not suitable for low voltage applications unless one can account with non standard depletion transistors for Mp1 in order to reduce the required total headroom voltage.

Figure 2 shows a low voltage implementation of the circuit, wherein low voltage cascode PMOS mirrors are needed. This configuration is more suitable low voltage circuits implemented in standard technologies. However, the bias voltage of cascode PMOS transistor should feature acceptable stability against Temperature and Power Supply variations. For this reason, the Cascode PMOS Bias Circuit, comprising two NMOS transistors, is implemented as shown in the latter figure. If (W/L)M5=(W/L)M6, thus VgsM6 = VBG, given that both transistors convey the same current. In practice one should set (W/L)M5 ¹ (W/L)M6 for Body and Early effects compensation. Eve...