Method for timing -enhanced and -driven ECC (error correction code) generation with simultaneous data formating
Original Publication Date: 2009-May-28
Included in the Prior Art Database: 2009-May-28
Method for timing-enhanced and -driven ECC generation with simultaneous data formatting. Using the delay consumed for formatting to not only calculate the ECC value of the unchanged input in parallel but also to predict a correction value for the ECC bits, based on the formatting operation performed. This enables w/ one additional gate delay the ability to protect data in a timing sensitive environment. Formatting operations may be little-/big-endian conversions, conversions between various floating-point formats, shift/rotate operations or general (sub-)value forcing like sign extend. While the approach is not limited to only one possible formatting being performed.