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Class A RF Power Amplifier Linearization Method - JTRS Disclosure Number: IPCOM000186059D
Original Publication Date: 2009-Aug-06
Included in the Prior Art Database: 2009-Aug-06
Document File: 4 page(s) / 223K

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Described is a class A RF power amplifier linearization method - JTRS.

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The CR1 JTRS Radio specification calls for a broadband linear integrated 50 mW RF class A amplifier to be fabricated using IBM* BiCMOS 7WL 3.3V technology. The load impedance is specified as 50 Ohms resistive. A typical class A output topology appears in Figure 1 below.

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The circuit functions as follows:

    Jbias is applied to the base of Q0 and produces a steady-state collector current of Jq at the collector of Q0 due to the dc current gain of Q0. An input sinusoidal input current, Jsin, modulates the base current of Q0 and thus the collector current of device Q0. "Class A" operation implies that the collector current of Q0 varies between 0 and (2 x Jq) by the action of Jsin. The collector current of Q0 never become zero but varies linearly around the value of Jq. Inductor L1 functions as a choke and may be considered a high impedance at the operating frequency and a short-circuit at dc.

    With a 50 Ohm load, a 50 mW output will require a voltage swing of +- 2.24 V (peak) sinusoidally across RL. The specification calls for a transformerless "class A" configuration so, under these conditions, the collector of Q0 will swing from 0.67 V to 5.93 volts (Vdd = 3.3V +- 10%). The only device in the BiCMOS 7WL menu that can support this voltage swing is the


       High Breakdown NPN bipolar transistor. It is this device that must be used as the output device in an integrated implementation.

The output characteristic of the NPN


device appears in Figure 2 below.

Superimposed on Figure 2 is a 50 Ohm load line. The output voltage, Vce, will traverse the load line as collector current in Q0 varies. Using 3.3V (+-10%) Vdd, at maximum current in Q0 Vce will drop to 0.67V and at minimum current Vce in Q0 will rise to 5.93V.


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    We observe from Figure 2, that the transfer function at less than 1V Vce and ranging to 6V will be nonlinear. Of particular concern is when Vce is less than 1 V where the output impedance of the device is low and the device approaches saturation. The spec calls for the output device to operate throughout the nonlinear regions to generate a distortionless 50 mW in RL. We see that the output characteristics of the HB device will cause severe distortion at the output voltage extremes in an open loop configuration. To meet an aggressive linearity-distortion spec of +17 dBm IIP3, a method was needed to linearize the output device. The "core idea" is to use a local feedback loop to linearize the transfer characteristic of the output bipolar transistor. The feedback loop is depicted below in Figure 3.


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    A current source, Jbias, applies a bias current to the collector of Q3 and the base of Q1. (