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Tunnel FET with Intermediate Tunneling Layer (TFITL)

IP.com Disclosure Number: IPCOM000187376D
Original Publication Date: 2009-Sep-03
Included in the Prior Art Database: 2009-Sep-03
Document File: 5 page(s) / 310K

Publishing Venue



A specially designed intermediate layer is inserted between the source and the channel in a tunneling field effect transistor in order to optimize the transmission coefficient for interband tunneling. This circumvents the well-known problems of low on-currents in tunneling FETs.

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In the past years the tunnel FET (TFET) [1] has provoked much interest as a possible candidate for low power electronics.
typically in an n-channel TFET electrons are injected from the top of the valence band in the source, into
the bottom of the conduction band in the channel, This process is illustrated for a simple PN junction in Fig. 1


Tunnel FET with Intermediate Tunneling Layer

Tunnel FET with Intermediate Tunneling LayerTunnel FET with Intermediate Tunneling Layer


the 'P' side represents the source and the 'N' side represents the channel of the TFET. In the 'on' state (a) electrons can
tunnel from the valence band in the channel to the conduction-band in the source.

Applying an increasing negative

gate voltage causes the tunneling distance to increase (b) and eventually the bands become uncrossed (c) shutting off
the current.

This structure can be used in a tunneling FET (TFET). The aim of the TFET is to achieve switching from 'on' to
'off' over a much smaller voltage range than the conventional FET. This is because the normally n-type source (for
an n-FET is replaced here by a p-type tunneling source where the top of the valence band cuts off the thermal tail,

which is present in the n-type

                   source, allowing one to achieve a sub threshold slope S of greater than 60 mV/dec at
room temperature,


S = [d(log10 ID ) / dVG ]-1, ID is the drain current and VG the

gate voltage.

A nanowire TFET

structure is shown in Fig. 2,

where the FET in this case consists of a wire comrising

semiconducting regions S1, S2 and
S3 and surrounded by a gate G separated by an insulating layer. S1 and S3 are heavily doped p-type and n-type in this
example. S2 and S3 are the same material but S2 in undoped.

A staggered band

heterojunction line-up [2] between S1 and S2 is used ,

where the bands in the source and channel are offset

allowing switching from 'on' state in Fig. 2 to the 'off' state in Fig. 3

with much smaller longitudinal electric fields than in a

homojunction. .

A positive voltage

applied to the gate turns the FET ON as shown in Fig. 3, permitting electrons to tunnel from the source into the channel
region, as indicated by the arrow. In the OFF state, shown in Fig. 4, the bands are uncrossed as in the diode
example of Fig. 1. Some undesired leakage current mechanisms are shown in Fig. 4


     (a) shows carrier excitation
to the conduction band of the channel, (b) shows direct tunneling from source to drain and (c) shows band-to-band tunneling
between channel and drain. Note that band bending in channel and source regions reduces the amount of
designed band offset (a) for a given on-current so degrading the on-off current ratio of


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the FET.

Also, the direct tunneling

component (b) places conflicting requirements of the effective mass of the electrons in region S2, since a small effect...