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A Simple Method to Blink and Fade (Increase/Decease) an Indicator Intensity by using a digital counter Disclosure Number: IPCOM000189371D
Original Publication Date: 2009-Nov-06
Included in the Prior Art Database: 2009-Nov-06
Document File: 4 page(s) / 97K

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Described is a technique that can be used to fade and blink an LED to indicate a system sleep state. This method can be implemented by using simple combinatory logic.

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A Simple Method to Blink and Fade (Increase/Decease) an Indicator Intensity by using a digital counter

The most intuitive method to indicate a system's sleep state is to slowly blink the power indicator LED while fading the brightness between states. Some analog and digital methods of implementing this function are:

Analog Method: Use a 555 timers or an operational amplifier to drive the indicator/LED. The intensity fade will be controlled by a RC Circuit. A concern is that the RC time constant could vary by more than 40% and this variation may be noticeable in the intensity of the indicator. The duty cycle would also be controlled by an RC with the same concerns as above.

Digital Method: Control the intensity by modulating the LED's on/off rate. This could get complex and may need to be controlled by a small microcontroller.



      Digital: A digital-to-analog converter can also be used but will be more costly and it will consume more space then any of the above.



      Digital: A digitally controlled variable resistor in series with an LED can be used to vary the light intensity. These types of devices are usually controlled by I2C which would dictate the need for a microcontroller.

The above techniques will require extra parts. The analog technique may not be precise enough. The digital technique may be costly and spacey to implement.

Disclosed is a technique that addresses the above issues by utilizing simple combinatory logic that can be integrated into an existing CPLD. The core circuit is an n-bit counter with open collector outputs attached to a simple resistor network. The other end of the resistor network will attached to a LED and a voltage source. The resistor network will source current through the LED that it proportional to the binary output of the counter. Since this technique can be implemented with an up/down counter and a toggle it can be efficiently contained in a CPLD. The size and frequency of the counter can be tuned to the requirement. Reference the Figures 1 and 2.

The basi...