Browse Prior Art Database

Method of Modeling Distance-Dependent Device Mismatch

IP.com Disclosure Number: IPCOM000190070D
Original Publication Date: 2009-Nov-16
Included in the Prior Art Database: 2009-Nov-16
Document File: 5 page(s) / 59K

IBM

Abstract

Disclosed is a method of modeling distance-dependent semiconductor device mismatch. Our method of modeling distance-dependent device mismatch leads to a much simpler solution for a statistical variable whose standard deviation does not vary with its distances to other devices, and the solution can correctly model a distance-dependent mismatch behavior among three or more devices simultaneously.

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Page 1 of 5

Method of Modeling Distance-Dependent Device Mismatch

Background. In semiconductor processes and devices as well as in analog circuits, identically designed devices placed nearby or placed with a distance show a certain amount of mismatch statistically, and the amount of mismatch increases with the separation between two concerned devices. Semiconductor device mismatch examples include FET channel length, FET threshold voltage, FET drain current, diffused or poly resistor's resistance value, MIMCAP's capacitance value, VNCAP (BEOL metal wires formed capacitor) capacitance values, ring oscillator's

period/speed, other logic circuits (

NAND,

NO

R

, etc)

period. Device mismatch is a limiting

factor for the performance/benchmark of many analog circuits, such as analog-to-digital converters or digital-to-analog converters. Including device mismatch in device and/or circuit models is very important for many analog circuits.

Pelgrom's model on the matching of a process parameter

P

(e.g., MOS transistor's drain current, diffused or poly resistor's resistance, metal-insulator-metal capacitor's capacitance, metal finger capacitor's capacitance) between two circuit elements (e.g., transistors, resistors, or capacitors)
is given by the equation [1]:

σ( 2

2

2

A

P +

P

2Δij D

S

)=WL

P

ij

, (1.1)

2

P

ij ) is the variance of the difference, Δ

P

ij =

where σ

P

i

P

j

, of parameter

P

between the i th and

j

and S

P

are the area and distance proportionality constants for parameter

P

, W and

L

th

devices,

A

P

th

devices (see Fig.

are the dimensions of each device, and

D

ij is the distance between the i th and

j

1).

Fig. 1. Identical devices are at different location on a chip.

References:

[1] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors",

IEEE

J. Solid-State Circuits

, vol. 24, 1433-1439 (1989).

Prior art. When not all devices are laid out in close proximity, some or all

D

ij

's are large, and thus the amount of device mismatch depends on device distance in general. For distance-dependent mismatch, the prior-art semiconductor device/compact/SPICE models are of the form

.

,

3

,

2

,

1

,

)

( 2

2

μ (1.2) where

= i

D

S

g

G

P P

m

i

G

i σ

+

σ

+

1 L

=

+

2

0

2

μ

is the mean value of the parameter

P

, each of G and

g

i , i = 1, 2, 3, …, is an independent

stochastic/random variable of mean zero and standard deviation one,

1

Page 2 of 5

σm =

AP

WL

0

D

is a model instance parameter for specifying a distance, and σ

G

is a tolerance parameter associated with the systematic variation component G of the parameter

P

. The variance of

P

i

in prior-art models is

( 2

2

2 L

=

+

+

=

i

D

S

P P

m

G

i σ

μ

)

σ

2

1

(

2

0

)

,

,

1

,

2

,

3

, (1.4) which now depends on model's instance parameter

D

2

. This is not correct. There...