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Modeling Input Slew and Output Load Dependent Input Pin Capacitance of a CMOS Gate using RC-Branch Trees Disclosure Number: IPCOM000190360D
Original Publication Date: 2009-Nov-25
Included in the Prior Art Database: 2009-Nov-25

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At advanced technology nodes, the excessive pessimism in static timing analysis tools has become a bottleneck for TAT of designing chips. It has become utmost important to improve the accuracy of sign-off timing analysis tools. The receiver gate in a delay stage in static timing analysis has traditionally been modeled as a lumped capacitance. But it has been observed that the receiver gate can no-longer be modeled as a single lumped cap. The charge flowing into the input pin of the receiver is dependent on the loading and driving conditions of the gate. We have observed that the input capacitance of receiver gate depends as much as 55% on the input slew and 25% on the output load. All the existing solutions are either iterative in their approach or doesn't fit well into the existing Static and Statitistical Timing Analysis engines. The iterative approaches causes huge increase in runtime and memory of the timing analysis tool.

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Modeling Input Slew and Output Load Dependent Input Pin Capacitance of a CMOS Gate using RC-Branch Trees


on its

driving and loading conditions. Traditionally this nonlinear dependency has been ignored and input pin capacitance has been modeled as a lumped capacitance. We have observed that at 65nm technology the pin capacitance can vary as much as 55% with the input slew and 25% with the output load. These variations cannot be ignored for accurate timing analysis. In this paper we propose a RC-Tree model to capture this nonlinear dependency. This model can be incorporated into delay calculation engine of STA by simply attaching it to interconnect parasitic network. Error in our model has shown to be less than 2% for majority of the cases. Our technique does not require any iterations to consider the nonlinear capacitance during delay calculation in STA.



tatic Timing Analysis has been used successfully to verify the performance of the designs with millions of gates. The block based algorithms in STA tools have enabled them to keep runtime and memory consumption under practical limits and expanded their usage to multimillion gate designs. Shrinking geometries have been posing new challenges to the accuracy of Static Timing Tools. Traditionally the design community has used pessimistic design margins to deal with these inaccuracies at smaller geometries.

    The demand for faster time to market has forced design and EDA community to revisit the traditional design margin approach. It has been observed that this guard-banding has resulted in unrealistic pessimism in the current static timing analysis tools and methodologies, resulting in very time consuming timing closure process. Due to these reasons, need for more accurate modeling of cell and interconnect in timing analysis tools has become very important.

    Various current source models have been proposed to accurately model a CMOS Driver gate of a delay stage shown in figure 1.


Typically the receiver of a delay stage is modeled as a lumped capacitance. Timing analysis tools use separate lumped input pin capacitances for early/late analysis and for rise/fall input waveforms. Due to large miller effect at lower process nodes, this approach is no longer feasible. Reference [1] demonstrated the nonlinearity of input capacitance with driving and

Parasitic RC





The input pin capacitance of a CMOS


ate has nonlinear dependenc


ot much research has been done to model the receive



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Fig 1

loading conditions and proposed an equivalent capacitance model to reduce the pessimism in traditional lumped capacitance model. But the paper did not consider the nonlinear dependency of input capacitance on input slew and output load. References [4,5] talk about this problem, but they do not propose a solution.

    Industry standard c...