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Using a mask to block the wakeup of dependants of already-issued instructions Disclosure Number: IPCOM000193322D
Original Publication Date: 2010-Feb-18
Included in the Prior Art Database: 2010-Feb-18
Document File: 1 page(s) / 21K

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In a conventional 2-stage dependence-matrix scheduler, the first stage is for waking up instructions using a dependence matrix and the second stage is for selecting a subset of ready instructions for execution. The output of the select circuit sets the latches that feed the dependence matrix. To handle multi-cycle instructions, there is a shift register for each instruction that denotes the latency of the instruction. The setting of the Available line will be delayed according to the shift register value.

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Using a mask to block the wakeup of dependants of already -issued instructions

If the two stages take one cycle each, in a conventional queue design, instructions will wake up their dependents as if they have a 2-cycle latency. However, multi-cycle instructions must delay setting Available lines or they will wake up their consumers too early. This means the output of the select logic does not directly feed the latches controlling the Available lines; there is combinatorial logic in front of these latches to block setting the Available lines at issue, and allow setting the Available lines at the appropriate time. The combinatorial logic adds to the critical path through the select logic, thus potentially increasing the cycle time.

In this disclosure, the Available latches are set directly from the output of the select logic. The combinatorial logic is not needed. The Available Mask is ANDed with the Available latches to form the Available lines feeding the dependence matrix. For an instruction with an issue-to-issue latency less than or equal to the time it takes to wake up and select an instruction, the bit of the Available Mask corresponding to the instruction's result is initialized to 1 at dispatch time. For longer-latency instructions, bits of the Mask are initialized to 0 at dispatch time. They are set to 1 after the instruction has been selected for execution, off the critical path of the select logic.