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Memory Controller Mode for Optimally Scheduling Reads/Writes Around zq Calibration Commands in a Multi Rank Memory Subsystem

IP.com Disclosure Number: IPCOM000194664D
Publication Date: 2010-Apr-06
Document File: 1 page(s) / 26K

Publishing Venue

The IP.com Prior Art Database


When running ZQCal commands for DDR3 periodic calibration, there is an opportunity for memory controllers to aggressively schedule commands after the ZQCal. The memory controller can initiate the subsequent command a number of cycles before the ZQCal has finished, based on the memory bus, rank, and speed bin.

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DDR3 SDRAMs support zq calibration (ZQCal) commands for periodic calibration of the output driver impedance for data (DQ) and data strobe (DQS) pins. This is done to compensate for voltage and thermal variations in the system over time. There are different ZQCal commands, some requiring as many as 256 memory clocks but, more typically, only 64 memory clocks during normal system operation. The DRAM specification indicates that no commands may be issued to the same memory rank while a ZQCal command is in progress. It also states that, if there are other ranks on the same memory bus, the data strobes from the other ranks must not switch while the ZQCal command is in progress.

    DRAMs support many different modes and timings that differ between various SPEED bins. With varying speed bins, the time from command launch to receipt of data on a read is dictated by both tRCD (RAS to CAS delay) and tCL (CAS Latency). Similarly, the time from command launch to data launch is dictated by tCWL (CAS write latency).

    Because the data strobes and data switching are not coincident with the command launch, there is opportunity to allow command launch of a read or write command to another memory rank on the same memory bus without having to wait for the ZQCal to complete to a first rank. Additionally, the number of cycles by which the command can be launched prior to the completion of ZQCal increases as DRAM speed bin decreas...