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Cost-Benefit Analysis for Optimizing Test Pattern Insertion

IP.com Disclosure Number: IPCOM000197731D
Publication Date: 2010-Jul-20

Publishing Venue

The IP.com Prior Art Database

Abstract

A method is provided to optimize insertion of test patterns executed on semiconductor chips. Test patterns are executed on a sample set of semiconductor chips and results of the executed test patterns are analyzed. The analysis identifies redundant and ineffective test patterns. The redundant and ineffective test patterns are then removed, thereby saving cost associated with test time, test equipment usage, etc.