Method and System for Fabricating Non-Volatile Floating Gate Structure with Superior Charge Retention
Publication Date: 2010-Jul-20
The IP.com Prior Art Database
A method for fabricating a single poly-silicon layer non-volatile floating gate structure with improved charge retention is disclosed. By incorporating a thick top silicon oxide spacer between the floating gate poly-silicon and the silicon nitride dielectric layer, charge retention is increased > 2000X at a use temperature of 250C.
Method and System for Fabricating Non -Volatile Floating Gate Structure with Superior Charge Retention
Disclosed is a method and system for fabricating a single poly-silicon layer non-volatile floating gate structure with improved charge retention.
Typically, a Complementary Metal-Oxide-Semiconductor (CMOS) process flow includes processing at the top surface of a poly-silicon gate electrode. This processing has a significant effect on the non-volatile floating gate charge retention. Therefore, spacer silicon oxide/nitride structures are used on the top and upper sidewalls of the floating gate polysilicon that significantly reduce charge leakage.
Fig. 1 illustrates the use of a thick silicon oxide spacer on the top and upper sidewalls of the floating gate polysilicon for significantly reducing the charge leakage. The thickness of the silicon oxide layer, is increased from 50A to 150A, with a resultant improvement in charge retention of greater than 2000X. Specifically, the charge retention at a use temperature of 250C, is increased from 50 hours to greater than 10 years. The mechanism by which charge is retained through the use of a thicker silicon oxide layer is explained by a critical silicon oxide thickness, whereby charge written to the
poly-silicon, does not leak to the surrounding silicon nitride dielectric layer. If the charge leaks to this silicon nitride layer, it is dissipated to traps in the s...