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Method and Structure for Forming Integrated Circuit with Controlled-Shape Backside Contact Patterns for 3D Integration

IP.com Disclosure Number: IPCOM000197767D
Publication Date: 2010-Jul-21

Publishing Venue

The IP.com Prior Art Database

Abstract

A method for forming contact patterns at wafer backside for 3D integration is disclosed. The method includes (1) forming FEOL devices at front side of a semiconductor wafer; (2) bonding the semiconductor substrate to a carrier; (3) thinning the wafer backside; (3) forming contacts from wafer backside by lithography, RIE, and filling.