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3D Pb-free Package for Enhanced Electromigration Reliability Disclosure Number: IPCOM000198328D
Publication Date: 2010-Aug-04
Document File: 3 page(s) / 69K

Publishing Venue

The Prior Art Database


A 3D Pb-free package for enhanced electromigration reliability is disclosed.

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3D Pb-free Package for Enhanced Electromigration Reliability

Disclosed is a 3D Pb-free package for enhanced electromigration reliability.

Although various Pb-free solder connections exist, for high-end servers, there are two technical challenges faced when high-Pb bumps are replaced with a Pb-free bump such as Sn/Ag solder. Server processor die are high-power, and require currents up to 250mA per power C4 (or bump). Under such high currents and an operating temperature of 100-120°C, a phenomenon known as electromigration (EM) can take place in metal conductors and solder connections. The requirement for EM reliability for future high-end servers has been established as 250mA max current per C4 at 100C to have a life of 100,000 power-on-hours (KPOH) or field life. However, the EM data for typical Sn/Ag bumps used with 75µm bump is that it only supports about 110mA at 100C for 100KPOH.

Further, in the case of server connections, for both the Si-interposer and Flip-Chip Plastic Ball Grid Array (FC-PBGA), the surface finish is typically Ni/Au unlike standard PBGA finish of Cu + Solder-on-pad such as, SAC 305 Pb-free alloy. The Ni/Au finish for the PBGA is driven by the requirements of Land-grid-array (LGA) for connecting the package to the card. LGA such as, spring-contacts or "fuzz buttons" typically require a Ni/Au finish to maintain good electrical contacts in field life in a typical office environment. Considering Fig 1, the presence of a Ni barrier on both sides of a solder

joint for both the die to Through Silicon Via (TSV) carrier, and TSV carrier to laminate

LGA package, further degrades the EM performance.


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Figure 1

The method disclosed herein solves the EM challenge in server packages where Pb-free solder use will be required for both chip to package or chip to TSV carrier, and TSV to a package connections.

The method disclosed herein involves replacing solder bumps between die and TSV and/or TSV to package with Cu-pillars. As a result, there is no solder to Ni barrier interface on both sides of the solder. This feature along with the current spreading ability of a Cu-pillar compared to solder in small via region of the Under Bump Metallurgy (UBM

             (either on the die or on the BSM side of the TSV carrier) improves EM life significantly.

Fig. 2 schematically illustrates a 3D Pb-free package for enhanced electromigration reliability. Here, both the processor die and the backside (BSM) of the TSV interposer carrier include Cu-pillars along with plated Sn/Ag solder instead of prior art which uses plated or C4NP type bumps. The UBM on the die does not have the Ni barrier. Similarly, the BSM side of the interposer is also free of the Ni barrier. The Ni barrier is not required since the tall Cu-pillars are far away from the Sn/Ag plated solder used for

joining to TSM of the TSV interposer or the LGA package. As a result, there is no

Ni-barrier used as in the prior...