Browse Prior Art Database

%MPG% Voltage Stacking for Inherent Power Supply Down Conversion in Memory Subsystem Disclosure Number: IPCOM000199688D
Publication Date: 2010-Sep-14
Document File: 4 page(s) / 67K

Publishing Venue

The Prior Art Database


Voltage stacking of memory subsystem is described.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 96% of the total text.

Page 1 of 4

ȈȈ ˇ ˄ ˙ ˝ ˛ ˚ ˇ

~˛ˇ˛ ˚

~˛ˇ˛ ˚ ~˛ˇ˛ ˚

As memory power is increased, delivering the power is becoming a problem. The memory is generating higher and higher current consumption, so I-R drop is significant under the same resistance between the power source and the memory (see Figure 1). One conventional method shown in Figure 2 is to distribute higher voltage with smaller current at the near end of memory devices. But, the voltage down converter has less than 100% conversion efficiency, and it is not easy to mount the voltage down converter at some place near the memory device (or near the memory module, or on the memory module) where a lot of memory devices and modules are populated.

    This invention proposes to stack up semiconductor devices in supply voltage domain to automatically down convert higher voltage down to actual memory VDD. This technique requires that all those stacked devices would consume exactly same amount of current (or power) so that voltages would be equally divided. This statement is met when we apply this technique to memory devices because large number of memory devices in the same rank would perform exactly the same internal operation (see Figures 3-9).

ȈȈ ˇ ˄ ˙ ˝ ˛ ˚ ˇ

ȈȈ ˇ ˄ ˙ ˝ ˛ ˚ ˇ ȈȈ ˇ ˄ ˙ ˝ ˛ ˚ ˇ


[This page contains 2 pictures or other non-text objects]

Page 2 of 4


[This page contains 2 pictures or other non-text objects]

Page 3 of 4


[This page contains 3 pictures or other non-text...