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Method of Multi-Dimensional Performance Based Testing for Timing Sensitivities Disclosure Number: IPCOM000200131D
Publication Date: 2010-Sep-29
Document File: 3 page(s) / 43K

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Described here is a test method enabling effective testing of a multidimensional timing sensitivity while minimizing test time.

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Method of Multi-Dimensional Performance Based Testing for Timing Sensitivities

Circuit timing sensitivities are often sensitive to semiconductor processing variations and applied conditions such as temperature, voltage and frequency. If a chip timing sensitivity is relatively stable (independent of process variation for example), testing for said sensitivity is common using standard performance based tests with targeted patterns. However, if a timing sensitivity has know behavioral fluctuation for any reason, such as process variation, then the existing targeted patterns usually need to cover a wider range of applied conditions resulting longer test times and higher test costs.

Defined here a test method which queries the device under test (DUT) for one or more

parameters then uses this obtained information to define test with customized parameters which

will detect a functional fail mode over a sensitive operating range (such as a shmoo) specific to the DUT. Because this test is customized for each part, it can be optimized for effectiveness and minimized for test time, to protect both the customer and save test costs.

Information inherent to the particular DUT is obtained during test, this information may be

d, (like a ring oscillator measurement, or a flush delay measurement..etc),

parametric based like power consumption or other process parameter based metric. Once this

information is collected for the DUT, the Multi-Dimensional Test (MDT) can be customized to define what patterns, voltages, frequencies or other variables needed, in order to apply a test which reduces test time while targeting a sensitive operating area for a known fail mode which

protects the customer.

1. Read relevant information out of the chip, by running tests and seeing results, or by reading previously stored information which may have been recorded in some manner, like electronic chip id (ECID)

2. Use the information gathered to define a multidimensional test or tests to be run on the DUT. These specifics may include voltage, frequency,

patterns or any other relevant

performance base


3. Once the test is run, the pass/fail criteria may also be customizable by application usage

One example of how processing performance can affect a timing sensitivity in the voltage dimension is shown in Figure 1. In this figure it can be seen that the sensitive voltage window cor...