Method of FF Design with Asymmetric Clock Delay
Publication Date: 2010-Oct-27
The IP.com Prior Art Database
High performance requirement for modern IC's forces more aggressive design techniques, including useful clock skew.
High performance requirement for modern IC’s forces more aggressive design techniques, including useful clock skew.
Ø high performance requirement for modern IC’s forces more aggressive design techniques, including wide usage of useful clock skew
Ø main problem with useful clock skew implementation is tuning of clock tree and inserting/removing buffers in clock tree, that impacts its design and robustness
Ø while useful clock skew is applied for low amount of FF’s, it can be done with low amount of additional buffers, but for massive usage there is no simple robust methodology
Ø there is known trade-off for clock implementation inside FF:
Ø Some buffers on clock are good for buffering and reducing capacitance on clock input, but it causes additional delay on clock tree inside FF
Ø Direct connection of transfer gates to input clock reduces delay, but increases input capacitance
Ø One of above methods is selected for library design
Ø Proposal is to design FF’s in both approaches and thus to get FF’s with different delay of clock tree inside FF’s
Ø it will allow obvious useful clock skew implementation by selection appropriate FF’s and without any tuning of clock tree
Figure 1 shows using of different types of FF’s to resolve timing critical path.