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A novel area efficient performance enhancement circuit for IO design Disclosure Number: IPCOM000201569D
Publication Date: 2010-Nov-15

Publishing Venue

The Prior Art Database


Reduced core voltages for chips require most IO circuits for level translation to higher off-chip signal levels. IO pre-drivers that drive a final output stage, have control over delay, Di/Dt and frequency targets. This paper presents area efficient performance enhancement pre-driver circuits to address the various issues arising in IO circuits like frequency limitations, Di/Dt, Delay and power. This can be adopted in various IO designs including CMOS, HSTL & SSTL.

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A novel area efficient performance enhancement circuit for IO design

I. I

IOs serve in interfacing core circuits in a System on chip and signals originating in the core to external world devices. IO circuit consists of Transmitter - level shifter +

                                              re-drivers + output drivers & Receiver - Single ended/Differential. The pre-drivers drive the push-


                 ull stage can load pre-drivers causing frequency limitations and signal integrity issues (Pre-driver outputs may not swing fully leads to jitter). This paper demonstrate an adaptation to pre-drivers designs to meet high frequency with less delay and less Di/Dt (crossover current). Through a simple structural change, it is very effective in not only improving performance but also saves significant area per IO.

The next section describes the conventional and existing IO pre-drivers. Section III describes the proposed circuit. Section IV discusses comparative results.
***Have used SSTL class 2 IO for spectre simulation purpose.


A conventional CMOS push-


ull I/O that interfaces a 1.0V internal logic signal (A) to
2.5V off-chip CMOS bus (PAD) is shown in Fig 1. The core supply voltage (VDD) is 1.0V and the second supply (IO) voltage (DVDD) is 2.5V under nominal conditions. The signal OE (Output Enable) is used to tri-state the PAD when asserted LOW.

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Fig. 1: Conventional IO Driver

The level-shifters translate the 1.0V signals to 2.5V signals, which are given to the pre-drive

NAND and NOR gates. If OE is LOW, then the outputs of the NAND gates (G1 node) go HIGH

to turn OFF the Output driver PFETs and the outputs of the NOR gates (G2 node) go LOW to turn OFF the Output driver NFETs :PAD is tri-stated. The pre-driver output nodes, named G* in Fig.1 are slew controlled by resistors and/or device sizing of the pre-driver devices. The figure shows a simplified output stage with single transistors for pull-up and pull-down. In reality, there could be multiple fingers of the PFET and NFET output stage, controlled by G1* and G2* outputs respectively from the pre-driver. In this implementation one can imagine these multiple

pre-driver outputs (not shown) as taps off of the slew control resistors, so as to turn on/off the

output driver fingers (not shown) in a staggered fashion. Another implementation (not shown) could be to place the slew control resistor in between the pull-up and pull-down sections of the



ull output stage.

Conventional Pre-drivers are NAND (Turn on PFET Driver slowly) and NOR (Turn on NFET Driver slowly). Large Push-




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NAND and NOR pre-drive circuits.

In functional mode (when OE is HIGH), if A goes from LOW to HIGH, then the G2* nodes go LOW first and then the G1* nodes go LOW in sequence (G11 followed by G12 followed by G13 followed by G14). The OUTPUT DRIVER NFETs are turned OFF but the OUTPUT DRIVER PFETs are turned on in a staggered fashion, in order to...