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Digital Deglitching circuit for PSI and FSI clocks and other pervasive signals Disclosure Number: IPCOM000201793D
Publication Date: 2010-Nov-23
Document File: 1 page(s) / 410K

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The Prior Art Database


Described is a deglitching circuit having a delay that is of programmable duration. The delay is set to at least two times a longest anticipated glitch.

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The innovative circuit shown in the figure below will remove glitches associated with rising and falling edges of a signal. A delay vector (that is, having a given number of bits, each of which are programmable to "1" or "0") controls a duration of a programmable delay. An output of the circuit rises after a delay that is responsive to a value of the programmable delay vector; the output of the circuit falls after the delay that is responsive to the value of the delay vector. The programmable delay needs to be equal in duration to two times a duration of a glitch that is to be ignored. Extra margin may be included in the duration of the programmable delay.

Programmable Digital deglitch adder for packaging density ( less shielding in BSM)

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