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Apparatus for Aligning, Cooling, Powering Stacked Chips Disclosure Number: IPCOM000201796D
Publication Date: 2010-Nov-23
Document File: 3 page(s) / 36K

Publishing Venue

The Prior Art Database


This disclosure provides a method for combing thermal cooling, power distribution, and die alignment requirements through the usage of die holes and a "post". Using such post provides excellent chip alignments, robust power connections, increased thermal cooling, and large decoupling capacitance.

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This is the abbreviated version, containing approximately 53% of the total text.

Page 01 of 3


As we enter the era of vertically stacked chips connected by Through-Silicon-Vias (TSVs), improved methods of cooling, power distribution, and chip alignment are required.

    Various alignment techniques are available. Power can be distributed in a variety of ways. This invention provides a means of accomplishing all of these in a combined solution. The invention is to cut a hole in the dies to be stacked and stack them on a "post". The post provides an excellent means of alignment as both the holes and the post can be constructed to the required precision. The post can also be made into a means to supply power. The dies can connect their metal stack power supplies sideways to the post. The post can supply both GND and VDD as the post can further be split with an oxide insulator thus providing a conductive path on each side of the insulator.

    The post acts as an excellent heat sink. Much as "donut holes" provide a means of evenly cooking and cooling real bakery donuts, so can this technique be used to reduce temperature effects in the center of a stacked chip arrangement. The post can act as a temperature conducting path from the center of the stack to the outside. Additionally, if the post is connected in as a power supply, be it as VDD, GND, or both, it is connected then to all the respective FETs in the chip stack. This provides an excellent thermal connection as well as an electrical connection.

    Additionally, if the post is split between VDD and GND, it will act as a large decoupling capacitor. In short, our invention provides several benefits:

Chip alignment


Robust power connection as GND, VDD, or both.


Heat sink and thermal connection to the module heat sink.


Large decoupling capacitance if the post is split between VDD and GND


As a robust power connection, it can help reduce wiring density of power connections.


    Figures 1 and 2 portray a single post through the center of a chip-stack. The gap between the dies and the post is exaggerated. It should be noted that this invention is not limited in number or size of posts. The post type (flavor) can be specif...