A Shiftable FIFO
Publication Date: 2010-Dec-01
The IP.com Prior Art Database
A shiftable FIFO is proposed here, which can handle different data for multiple applications. Other than normal FIFO, data can be written to the middle of the queue, or read from the middle of the queue. As the result of that, multiple function modules/engines can work with one FIFO, it can reduce internal memory size and increase the system performance.
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A Shiftable FIFO
For normal FIFO, data is stored from the top,
. the data in a FIFO are used for the same application, sometimes there are more than one kind of data for different purposes .
For example, there are many commands outside, Before these commands fetched, the commands' type are unknown, in order to reduce the external memory access's times, the commands will be read as much as possible and store them in a shared internal FIFO, if there are two kinds of commands, one is for encode, the other is for decode. and there are an encode engine and a decode engine too, the encode and decode engines can work parallelly. If encode engine is busy while decode engine is available, but at the same time the current command in the bottom is an encode command and the next command is decode , if normal FIFO used, only after the encode command fetched, the decode command can be read, so the decode engine can not be kicked off. It
will decrease the system performance
while fetched from the bottom
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Of course, two FIFO(one for encode, and one for decode) can be used to solve the problem too, but a new problem will occur. In the worst case, if encode FIFO is full,
't know the types of the commands in the external memory, so it can not fetch any new commands to the internal FIFOs. So, the decode engine can not be kicked off too. the system performance will be decreased too.
In order to solve these problems, a shiftable FIFO is presented here.
For shiftable FIFO, it have a bottom pointer and a top pointer. In addition, in order to separate different data, for each kind of data, it has a individual bottom pointer and a individual top pointer. For the example described above, it has a bottom pointer register, a top point register, an encode bottom pointer register, an encode top register, a decode bottom pointer register, a decode top register. so available space in the FIFO can be known through the bottom pointer register and the top pointer register . the encode commands location can be known through the encode bottom pointer register and the encode top pointer register . in the same the
while decode FIFO empty. Because the internal controller doesn
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decode command location can be known too. so the bottom encode command and the bottom decode command can be read at the same time. the encode engine and the decode engine can be work in parallel.
After the command read out
, the encode/decode commands can be shifted to merge the space between the encode commands and the decode commands . When some commands prepared to store in the FIFO, the encode/decode commands will be sh...