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Process for Semiconductor Back-end-of-line (BEOL) Capacitance Reduction Disclosure Number: IPCOM000206437D
Publication Date: 2011-Apr-26
Document File: 4 page(s) / 115K

Publishing Venue

The Prior Art Database


A process flow for an airgap process is disclosed for reducing capacitance by employing generic masks instead of custom masks for every level.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 51% of the total text.

Page 01 of 4

Process for Semiconductor Back -end-of-line (BEOL) Capacitance Reduction

Disclosed is a process flow for an airgap process for reducing capacitance by employing generic masks instead of custom masks for every level.

In accordance with the process, trenches which eventually result in keyhole voids are made by using a generic mask with maximum or near maximum stepper field size. The generic mask is composed entirely of a simple line space array. The generic mask can be used for every wiring level with the same groundrules (for instance, every Mx level in a design). In an instance, the generic mask can be used for different types of wiring levels such as 1x levels and 1.3x levels.

Sequence of process steps is as follows after the standard CMP, deposition of CoWP cap, and deposition of dielectric cap material:

1) Coat wafer with negative photoresist (in addition to appropriate underlayers(s) if needed for a multilayer resist process)

2) On the lithography tool, shutter down the generic mask field so that the negative resist is exposed with the line/ space array over the entire chip, in such a way that the line/space array is orthogonal to most of the wiring which was formed in the prior Cu CMP step. Also, it is acceptable to expose exterior dicing channels at this point since they are re-exposed in subsequent step, but the x and y stepper shutters should be used in such a way as to ensure that when one functional chip is exposed with the line/space array, none of the adjacent functional chips are exposed in the same shot.

3) Expose the exterior dicing channels by shuttering down a clear glass mask (or use no mask). The negative resist in the dicing channels can therefore be insolubilized by exposing two rectangular areas per field - one on the top or bottom of the functional chip, and one on the left or right of the functional chip, as shown in figure 1.


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Figure 1

4) Expose the chip with the next level via pattern, properly aligned. The resist should be exposed with the via pattern so as to insolubilize it in the areas where the next level vias come down, thus defining trench "keep out" regions as shown in figure 2.

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Figure 2


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The dose used should essentially be an over exposure (high dose) with the via pattern in this step, such that for each via, an area larger than the via contact area is insolubilized. Because of the overexposure, overlay is not as critical as for a regular via level exposure. Rather than usin...