Mechanism and Method for Cascading Access to Chip Registers Using Multiple Interfaces
Publication Date: 2011-Sep-20
The IP.com Prior Art Database
Described is a mechanism for firmware access of chip hardware registers is provided which uses multiple access protocols for robust, reliable operation while presenting a single seamless interface to the user in which failover access protocols are automatically activated if errors occur thus providing unprecedented ease-of-use.
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In the development of a particular electronic system:
1. Hardware engineers solved the problem of ubiquitous chip-level data access for internal status and configuration by providing a load/store mechanism that uses network packets for transferring internal register information.
2. During a network-level hardware failure, this mechanism of register access is not always available. Analysis of the chip by Reliability, Accessibility, Serviceability (RAS) code may not be able to access a chip's registers using the network packet load/store mechanism, yet register access must be available to diagnose and potentially recover from the failure.
3. Alternative register access mechanisms are provided to address this problem through the PCIe and I2C busses. Thus, there are three mechanisms for register access: the fast, standard ethernet mechanism, and the PCIe and slower I2C mechanisms.
4. Error recovery may require multiple register access mechanisms and may require a change in access mechanism in the middle of a recovery procedure. This requires either separate routines for each recovery scenario corresponding to each register access method or a continual verification that at least one register access method is still operational after any register access failure. This can result in a significant performance hit and code bloat to handle these cases.
A mechanism is needed that provides dynamic switching between the various register access methods such that the internal mechanism used to access the register data is transparent to the clients. During failures, this disclosure allows several interfaces to be used in a serial fashion with the most common and fastest interface (network load/store) being first and I2C being last (as it is relatively slow). A single interface is provided to clients for register access in which register access mechanisms are arranged hierarchically. Any register access failures are maintained within the interface instantiation and cause the next lower (and slower) register access mechanism to be activated as the primary register access method. This provides a single register access interface to all clients that use whichever register access method is appropriate for the error state of the machine. Multiple code paths corresponding to each register access mechanism and multiple tests for register access errors are averted since the appropriate access method is automatically activated as need arises within a register access code encapsulation.
Once a failure is identified by internal hardware "error checkers", the error triggers an interrupt and a packet is sent to the controlling processor in the Harrier system. If the interrupt has malfunctioned, then the processor queries every second for a failed chip. Once either the interrupt packet or a successful query has occurred in the system, RAS code proceeds to analyze the chips in the system for the given event. Primarily, the RAS code reads all pertinent regi...