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Novel method to reduce dynamic power by box movement Disclosure Number: IPCOM000213666D
Publication Date: 2011-Dec-30
Document File: 3 page(s) / 33K

Publishing Venue

The Prior Art Database


Disclosed is a method to reduce the power consumed by high performance chips by moving the gate in order to minimize the dynamic power contribution due to wire capacitance.

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Novel method to reduce dynamic power by box movement

Power consumed by high performance chips is gathering lot of importance as developers advance the technology node. One of the major components of power is dynamic power, which is the power dissipated when a gate switches its output from high to low or low to high. Cell delay is reduced with new technology nodes. However, the Resistor Capacitor (RC) component of net delay remains almost constant as wires do not shrink. Now wire capacitance is also becoming a dominant factor in overall dynamic power.

This disclosure describes a new technique to reduce the power by moving the gate so that the dynamic power contribution due to wire capacitance is minimized. This invention is in synthesis flow using Electric Design Automation (EDA) tools for physical design to optimize power in Very Large Scale Integration (VLSI) chips.

No known prior art exists which reduces the power consumed by the design by moving the gates around.

Dynamic power consumed by a gate is proportional to the product of capacitive load driven by the gate and switching rate. Capacitive load includes the output wire capacitance and the capacitance of sink gates. The switching rate of a gate is a factor that gives the switching probability at the output of the gate. Moving a box closer to the sink or source reduces the wire capacitance of the output or input net respectively. The new approach is to reduce the dynamic power by moving the gates. Moving a gate to a suitable location reduces the product of switching factor and wire capacitance on the input and output section of the gate. This in turn reduces the dynamic power and, hence, the overall power of the design.

The dynamic power of a gate is measured as 0.5 * C * V2 * f * a

Where C = capacitance driven by the gate

V = supply voltage

f = frequency

a = activity or switching rate

Wire capacitance also...