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Method for Statistical Timing Analysis with Data Override Disclosure Number: IPCOM000215252D
Publication Date: 2012-Feb-23
Document File: 9 page(s) / 371K

Publishing Venue

The Prior Art Database


This invention is to perform timing analysis with data override:1) Perform post-clock timing without data paths impacts, so that post-clock timing can be run in very early stage even when data paths are not well optimized;2) Accurately check if clock quality meets the requirement of final timing closure;3) Separate data paths and clock trees issues, reduce TAT and complex, enhance parallelism;

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Method for Statistical Timing Analysis with Data Override

In traditional ASIC design process:

1. clock stage: clock iterations include clock implementation, clock timing and clock refines, when clock meets clock spec. , then move on to next stage of iterations;

2. deterministic STA stage: deterministic STA iterations include deterministic timing analysis, data paths optimization, when deterministic STA reports are in good shape, then move on to next stage of iterations;

3. statistical STA stage: statistical STA iterations include statistical timing analysis, timing violation corrections on data paths, iterations go on until timing closure.

The problem of traditional method is: There are cases that clock quality got worse and causes huge number of timing violations only in SSTA stage, so that integrated circuit engineers have to go back to clock stage to refine clock. It will impact design schedule significantly. Therefore, designers need to verify if current clock quality meets the design criteria of final timing closure in earlier stage even before all data paths are well optimized. However, currently, a timer supports above requirement doesn't exist in the EDA industry.


Clock Iterations

Deterministic STA Iterations

Statistical STA Iterations

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Clock Iterations

Deterministic STA Iterations

Statistical STA Iterations

There are some prior arts which represent classic existing method in traditional process:

US 6550044 B1 2003 "METHOD IN INTEGRATING CLOCK TREE SYNTHESIS AND TIMING OPTIMIZATION FOR AN INTEGRATED CIRCUIT DESIGN", find timing violations by performing timing analysis, then performing clock skew optimization to correct timing violations discovered by the timing analysis;US7546567 B2 2009 "METHOD AND APPARATUS FOR GENERATING A VARIATION-TOLERANT CLOCK-TREE FOR AN INTEGRATED CIRCUIT CHIP", calculate timing slack on placed design netlist to compute timing criticality so that clock tree skew can be optimized accordingly, a timing criticality can be computed based on the slack described as (T-t)-(delta+d), T is the clock period, t is the setup time of the capturer, and the d is the data path delay which can be obtained from the placed design netlist. US 2010/0070941 "ACHIEVING CLOCK TIMING CLOSURE IN DESIGNING AND INTEGRATED CIRCUIT", timing violations are determined for clock gates generated by the virtual clock buffering;However, they cannot solve above problem, so why the methods in prior arts cannot solve the problems described above? In SSTA timing, slack cannot be worked out by traditional manual simple calculation:


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SSTA timing can only be run when data paths are fully optimized and deterministic timing in good shape in traditional flow, one reason is that all the variables vary in a range, while early stage design cannot ensure the rangeis not exceeded, another reason is the run time consideration;Real case 1: S chip implemented > 1000 clock trees and has complex clock structure, clock quali...