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Governor for Delay Elements During Periodic Calibrations

IP.com Disclosure Number: IPCOM000215269D
Publication Date: 2012-Feb-23
Document File: 2 page(s) / 30K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a methodology to use hardware monitors in conjunction with periodic DRAM calibration data to dynamically predict errors and re-allocate system resources during runtime.

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Governor for Delay Elements During Periodic Calibrations

Calibration is a function, either implemented in hardware or software or a combination of both, which uses delay elements or changes in signals' relationships in order to optimize a timed interface. Periodic calibration is used to re-center or re-optimize these delay elements and compensate for drift over time. These drifts could be caused by any number of things, such as frequency variations, voltage shifts, or temperature changes. This would normally require the hardware or software to perform re-calibration periodically to account for these changes and maintain system reliability. How often calibration is performed during runtime, as well as what triggers it, could be dictated by such things as timers but may also be triggered by thresholds of errors, temperature, changes in calibration results over time, or some other similar metric. Which metric, sensor, or time-based trigger is used depends on the system design and architecture as well as its use in the customer environment. Because of the design of memory controllers as well as memory busses and architecture, many components of the memory subsystem are required to operate correctly in order for these periodic or runtime calibrations to obtain accurate results. Problems could occur in parts of the memory subsystem that are unique to the path from the memory controller to a particular set of DRAM modules, such as memory controller logic, the connections between the memory controller, and the DRAM, or the DRAM itself. Problems may also occur with components which aren't unique to a particular memory controller to DRAM path but are shared, such as connectors, loads from DRAM which share a bus with the targeted DRAM, and wiring that makes up the bus.

    As operating frequency of memory increases and bus stability and reliability becomes more challenging, methods to detect problems before they occur have become a vital part of the design of current and future computing systems. Also, various problems could occur in a memory subsystem which may affect the results of calibrations of a memory bus. Inaccuracies in calibration results could cause corruption of the integrity of the bus such as mis-centering or, worse, the results eventually diverging or "walking" away from an acceptable range. The motivation of this disclosure is to resolve these issues.

    This article describes a solution to the above described problems. The solution is a limiter or "governor" which monitors the results coming from the calibrations of the DRAM bus. This governor would watch the results from calibrations and compare them to acceptable results. These acceptable results could come from characterization results where limits could be determined by running wide spreads of hardware over various frequency, voltage, temperature, and process corners. Limits could then be established as absolute limits, where any results outside of set limits would be correcte...