CPK Based IO Timing Closure in STA to Reduce Yield Loss and Test time
Publication Date: 2012-Feb-29
The IP.com Prior Art Database
In any SoC design, IO timing (setup and hold timing) is met in STA (Static Timing Analysis) based on the hardware specification of the particular interface, with some pessimism. Many times it has been found or observed that even though IO timing is met in best and worst case corners, IO timing fails or is marginal when tested in Si across PVT. Also, the margin from IO timing check on ATE may not be sufficient for the production pattern to remove from the production flow, hence increase test time of SoC. Therefore, to aid this cause, “CPK based IO timing closure in STA” has been proposed, whereby IO timing is closed in the design phase, keeping required CPK in mind.